Simple , Fast and Synchronous Hybrid Scaling Scheme for the 8 - bit Moduli Set { 2 n − 1 , 2 n , 2 n + 1 }

This paper presents an optimized synchronous hybrid scaling scheme for the 8-bit moduli set {2 − 1,2,2 + 1}. Both Look-up-tables (LUTs) and modular adders are employed efficiently to generate the accurate scaled residues. Reverse conversion from residues to the original binary number is also computed in one residue channel without further hardware cost required. Xilinx device xc6slx4 − 3tqg144 has been used with maximum frequency of 120MHz. The implementation results show total 14.15mW on-chip-power consumption for a 8 × 8 input data in 21ns. Evaluation analysis in terms of complexity and delay shows merits of current design over both LUT and Fulladder (FA) based designs. It shows up to 95.38% savings on complexity over LUT based designs and 87.02% and 69.64% savings on unit gate delay over FA and LUT based designs, respectively.